View M68AW064F_1189856.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M68AW064F
1 Mbit (64K x16) 3.0V Asynchronous SRAM
FEATURES SUMMARY s SUPPLY VOLTAGE: 2.7 to 3.6V
s s
Figure 1. Packages
64K x 16 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIME: 55ns and 70ns LOW STANDBY CURRENT LOW VCC DATA RETENTION: 2.0V TRI-STATE COMMON I/O AUTOMATIC POWER DOWN
TFBGA48 (ZB) 6 x 8 solder balls
BGA
s s s s
April 2003
1/18
M68AW064F
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . 9 Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . 9 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 11. Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 12. Low V CC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Low V CC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TFBGA48 - 6 x 8 ball array, 0.75 mm pitch, Bottom View Package Outline . . . . . . . . . . . . . . . . . . 15 TFBGA48 - 6 x 8 ball array, 0.75 mm pitch, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . 15 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/18
M68AW064F
SUMMARY DESCRIPTION The M68AW064F is a 1 Mbit (1,048,576 bit) CMOS SRAM, organized as 65,536 words by 16 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This device has an au-
tomatic power-down feature, reducing the power consumption by over 99% when deselected. The M68AW064F is available in TFBGA48 (0.75 mm pitch) package.
Figure 2. Logic Diagram
VCC
Table 1. Signal Names
A0-A15 DQ0-DQ15 Address Inputs Data Input/Output Chip Enable Output Enable Write Enable Upper Byte Enable Input Lower Byte Enable Input Supply Voltage Ground Not Connected Internally
16 A0-A15 W
16 DQ0-DQ15
E G W UB
E G UB LB
M68AW064F
LB VCC VSS NC
VSS
AI04872b
3/18
M68AW064F
Figure 3. TFBGA Connections (Top view through package)
1 2 3 4 5 6
A
LB
G
A0
A1
A2
NC
B
DQ8
UB
A3
A4
E
DQ0
C
DQ9
DQ10
A5
A6
DQ1
DQ2
D
VSS
DQ11
NC
A7
DQ3
VCC
E
VCC
DQ12
NC
NC
DQ4
VSS
F
DQ14
DQ13
A14
A15
DQ5
DQ6
G
DQ15
NC
A12
A13
W
DQ7
H
NC
A8
A9
A10
A11
NC
AI04874
4/18
M68AW064F
Figure 4. Block Diagram
VCC VSS ROW DECODER A7 MEMORY ARRAY
A15
DQ15 UB
(8)
I/O CIRCUITS COLUMN DECODER
DQ0 LB
(8)
A0 (8) W E (8) LB G UB
A6
UB LB
AI04875
MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 2. Absolute Maximum Ratings
Symbol IO (1) TA TSTG VCC VIO (2) PD Output Current Ambient Operating Temperature Storage Temperature Supply Voltage Input or Output Voltage Power Dissipation Parameter
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Value 20 -55 to 125 -65 to 150 -0.5 to 4.6 -0.5 to VCC +0.5 1
Unit mA C C V V W
Note: 1. One output at a time, not to exceed 1 second duration. 2. Up to a maximum operating VCC of 3.6V only.
5/18
M68AW064F
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter VCC Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Output Circuit Protection Resistance (R1) Load Resistance (R2) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Input and Output Transition Timing Ref. Voltages M68AW064F 2.7 to 3.6V -40 to 85C 30 or 5pF 1.10k 1.55k 4ns 0 to VCC VCC/2 VOL = 0.3VCC; VOH = 0.7VCC
Figure 5. AC Measurement I/O Waveform
Figure 6. AC Measurement Load Circuit
VCC
I/O Timing Reference Voltage VCC VCC/2 0V DEVICE UNDER TEST
1N914
R1
OUT CL R2
I/O Transition Timing Reference Voltage VCC 0.7VCC 0.3VCC
AI04831
0V
CL includes JIG capacitance
AI03853
6/18
M68AW064F
Table 4. Capacitance
Symbol CIN COUT (3) Parameter(1,2) Input Capacitance on all pins (except DQ) Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 8 Unit pF pF
Note: 1. Sampled only, not 100% tested. 2. At TA = 25C, f = 1 MHz, VCC = 3.0V. 3. Outputs deselected.
Table 5. DC Characteristics
M68AW064F Symbol Parameter Test Condition Min ICC1 (1) ICC2 ISB (2) ILI ILO VIH VIL VOH VOL Operating Supply Current Operating Supply Current Standby Supply Current CMOS Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage VCC = 3.6V, f = 1/tAVAV, IOUT = 0mA VCC = 3.6V, f = 1MHz, IOUT = 0mA VCC = 3.6V, E VCC -0.15V, f = 0 0V VIN VCC 0V VOUT VCC (3) VCC = 2.7V VCC = 2.7V VCC = 2.7V, IOH = -1.0mA VCC = 2.7V, IOL = 2.1mA -1 -1 2.0 -0.3 2.2 0.4 55 Typ 7 1 0.5 Max 20 2 15 1 1 VCC + 0.3 0.4 -1 -1 2.0 -0.3 2.2 0.4 1 0.5 Min 70 Typ Max 15 2 15 1 1 VCC + 0.3 0.4 mA mA A A A V V V V Unit
Note: 1. Average AC current, cycling at tAVAV minimum. 2. All other Inputs at V IL 0.15V or V IH V CC -0.15V. 3. Output disabled.
7/18
M68AW064F
OPERATION The M68AW064F has a Chip Enable power down feature which invokes an automatic standby mode whenever either Chip Enable is de-asserted (E = High) or LB and UB are de-asserted (LB and UB = High). An Output Enable (G) signal provides Table 6. Operating Modes
Operation Deselected/Power-down Deselected/Power-down Lower Byte Read Lower Byte Write Output Disabled Output Disabled Upper Byte Read Upper Byte Write Word Read Word Write
Note: 1. X = VIH or VIL.
a high speed tri-state control, allowing fast read/ write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W, E, LB and UB as summarized in the Operating Modes table (see Table 6).
E VIH X VIL VIL VIL VIL VIL VIL VIL VIL
W X X VIH VIL X X VIH VIL VIH VIL
G X X VIL X VIH VIH VIL X VIL X
LB X VIH VIL VIL VIL X VIH VIH VIL VIL
UB X VIH VIH VIH X VIL VIL VIL VIL VIL
DQ0-DQ7 Hi-Z Hi-Z Data Output Data Input Hi-Z Hi-Z Hi-Z Hi-Z Data Output Data Input
DQ8-DQ15 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Data Output Data Input Data Output Data Input
Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Read Mode The M68AW064F is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip Enable (E) is asserted. This provides access to data from eight or sixteen, depending on the status of the signal UB and LB, of the 1,048,576 locations in the static memory array, specified by the 16 address inputs. Valid data will be available at the eight or sixteen output pins
within t AVQV after the last stable address, providing G is Low and E is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV, tGLQV or t BLQV) rather than the address. Data out may be indeterminate at tELQX, tGLQX and tBLQX but data lines will always be valid at tAVQV.
Figure 7. Address Controlled, Read Mode AC Waveforms
tAVAV A0-A15 tAVQV VALID tAXQX
DQ0-DQ15
DATA VALID
AI04876
Note: E = Low, G = Low, W = High, UB = Low and/or LB = Low.
8/18
M68AW064F
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.
tAVAV A0-A15 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ15 tBLQV UB, LB tBLQX
AI04877
VALID tAXQX tEHQZ
tGHQZ
VALID tBHQZ
Note: Write Enable (W) = High.
Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms
E, UB, LB ICC ISB tPU 50% tPD
AI03856
9/18
M68AW064F
Table 7. Read and Standby Mode AC Characteristics
M68AW064F Symbol Parameter Min. tAVAV tAVQV tAXQX tBHQZ (1, 2) tBLQV tBLQX tEHQZ (1, 2) tELQV tELQX tGHQZ (1, 2) tGLQV tGLQX tPD tPU Read Cycle Time Address Valid to Output Valid Data hold from address change Upper/Lower Byte Enable High to Output Hi-Z Upper/Lower Byte Enable Low to Output Valid Upper/Lower Byte Enable Low to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Chip Enable or UB/LB High to Power Down Chip Enable or UB/LB Low to Power Up 0 5 55 0 10 20 25 5 70 5 20 55 10 25 35 10 20 25 5 25 70 55 55 10 25 35 55 Max. Min. 70 70 70 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. At any given temperature and voltage condition, t GHQZ is less than tGLQX , tBHQZ is less than tBLQX and t EHQZ is less than tELQX for any given device. 2. CL = 5pF.
10/18
M68AW064F
Write Mode The M68AW064F is in the Write mode whenever the W and E are Low. Either the Chip Enable input (E) or the Write Enable input (W) must be deasserted during Address transitions for subsequent write cycles. When E (W) is Low, and UB or LB is Low, write cycle begins on the W (E)'s falling edge. Therefore, address setup time is referenced to Write Enable as tAVWL and to Chip Enable as tAVEL and is determined by the latter occurring edge.
The Write cycle can be terminated by the earlier rising edge of E or W. If the Output is enabled (E = Low, G = Low, LB or UB = Low), then W will return the outputs to high impedance within t WLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVEH before the rising edge of E, whichever occurs first, and remain valid for t WHDX and tEHDX respectively.
Figure 10. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A15 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ15 DATA INPUT tDVWH tBLWH UB, LB
AI04878
tWHAX
tWHQX
11/18
M68AW064F
Figure 11. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A15 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ15 DATA INPUT tDVEH tBLEH UB, LB
AI04879
tELEH
tEHAX
12/18
M68AW064F
Table 8. Write Mode AC Characteristics
M68AW064F Symbol Parameter Min tAVAV tAVEH tAVEL tAVWH tAVWL tBLEH tBLWH tDVEH tDVWH tEHAX tEHDX tELEH tWHAX tWHDX tWHQX (1) tWLQZ (1,2) tWLWH Write Cycle Time Address Valid to Chip Enable High Address valid to Chip Enable Low Address Valid to Write Enable High Address Valid to Write Enable Low LB, UB Low to Chip Enable High LB, UB Low to Write Enable High Input Valid to Chip Enable High Input Valid to Write Enable High Chip Enable High to Address Transition Chip enable High to Input Transition Chip Enable Low to Chip Enable High Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Output Transition Write Enable Low to Output Hi-Z Write Enable Low to Write Enable High 40 55 45 0 45 0 45 45 25 25 0 0 45 0 0 5 25 50 55 Max Min 70 60 0 60 0 60 60 30 30 0 0 60 0 0 5 25 70 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device. 2. CL = 5pF.
13/18
M68AW064F
Figure 12. Low VCC Data Retention AC Waveforms
DATA RETENTION MODE 3.6V VCC 3.3V
VDR > 2.0V tCDR E VDR - 0.2V E tR
AI04885
Table 9. Low V CC Data Retention Characteristics
Symbol Parameter Test Condition VCC = 2.0V, E VCC -0.3V, f = 0 (3) E VCC -0.3V, f = 0 tAVAV 0 E VCC -0.3V, f = 0 2.0 3.6 Min Typ 0.5 Max 15 Unit A ns ns V ICCDR (1) Supply Current (Data Retention) tCDR (1,2) tR (2) VDR (1) Chip Deselected to Data Retention Time Operation Recovery Time Supply Voltage (Data Retention)
Note: 1. All other Inputs at V IH VCC -0.2V or VIL 0.2V. 2. See Figure 12 for measurement points. Guaranteed but not tested. tAVAV is Read cycle time. 3. No input may exceed VCC +0.3V.
14/18
M68AW064F
PACKAGE MECHANICAL Figure 13. TFBGA48 - 6 x 8 ball array, 0.75 mm pitch, Bottom View Package Outline
D FD FE SD D1
SE BALL "A1" E E1 ddd
e e A A1 b A2
BGA-Z26
Note: Drawing is not to scale.
Table 10. TFBGA48 - 6 x 8 ball array, 0.75 mm pitch, Package Mechanical Data
Symbol A A1 A2 b D D1 ddd E E1 e FD FE SD SE 8.000 5.250 0.750 1.125 1.375 0.375 0.375 7.900 - - - - - - 6.000 3.750 0.350 5.900 - 0.260 0.900 0.450 6.100 - 0.100 8.100 - - - - - - 0.3150 0.2067 0.0295 0.0443 0.0541 0.0148 0.0148 0.3110 - - - - - - 0.2362 0.1476 0.0138 0.2323 - millimeters Typ Min Max 1.200 0.0102 0.0354 0.0177 0.2402 - 0.0039 0.3189 - - - - - - Typ inches Min Max 0.0472
15/18
M68AW064F
PART NUMBERING Table 11. Ordering Information Scheme
Example: Device Type M68 Mode A = Asynchronous Operating Voltage W = 2.7 to 3.6V Array Organization 064 = 1 Mbit (64K x16) Option 1 F = 1 Chip Enable; Standby from UB and LB Option 2 L = Low Leakage Speed Class 55 = 55ns 70 = 70ns Package ZB = TFBGA48: 0.75 mm pitch Operative Temperature 6 = -40 to 85 C Shipping T = Tape & Reel Packing M68AW064F L 55 ZB 6 T
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
16/18
M68AW064F
REVISION HISTORY Table 12. Document Revision History
Date July 2001 Version -01 First Issue Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 01 equals 1.0). Part number modified. 55ns speed class added. Maximum Standby Supply Current ISB modified. Values of certain AC Characteristics modified. Revision Details
09-Oct-2002
1.1
23-Apr-2003
1.2
17/18
M68AW064F
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
18/18

▲Up To Search▲

Price & Availability of M68AW064F

	To Download M68AW064F Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .